fig17

Figure 17. Grain boundary engineering enhances BDS to optimize ESP. (A) Experimental processing route and field-emission TEM images of [email protected] wt% SiO₂; inset shows FFT of the selected area. Step 1: Ce-doped SrTiO₃ powders synthesized via the solid-state method. Step 2: Pre-doped powders coated with varying amounts of tetraethoxysilane (TEOS) using the Stöber process. This figure is quoted with permission from Qi et al.^[144]; (B) Schematic of grain configurations in KNN and KNN@SiO₂ FE ceramics, alongside microstructure topography and elemental distributions of KNN-BZT@SiO₂ ceramics. This figure is quoted with permission from Huan et al.^[71]; (C) Schematic illustrating multiscale optimization strategies to achieve ultrahigh ESP in lead-free MLCC based on RFE 0.87BT-0.13Bi(Zn_2/3(Nb_0.85Ta_0.15)_1/3O₃@SiO₂ MLCCs. This figure is quoted with permission from Zhao et al.^[149]. BDS: Dielectric breakdown strength; ESP: energy storage performance; TEM: transmission electron microscopy; KNN: (K_0.5Na_0.5)NbO₃; FE: ferroelectric; MLCCs: multilayer ceramic capacitors; BZT: Ba(Zr_0.4Ti_0.6)O₃; RFE: relaxor ferroelectric; FFT: fast Fourier transform.