fig3

Figure 3. (A) Piezoresponse force microscopy (PFM) phase images of the erasable domain walls between two top electrodes. (B) I-V characteristics of the device in the presence ("1") and absence ("0") of domain walls. Reprinted with permission^[45]. Copyright 2017, American Association for the Advancement of Science. (C) A cross-sectional TEM imaging of thin (3.6 and 7.2 nm) dead layers at the Pt-LiNbO₃ interfaces, where a red dotted line indicates a persistent domain wall between two antiparallel polarizations. (D) I-V curves after poling at +/-12 V for the generation of antiparallel and parallel domain patterns within a two-terminal LN cell, respectively. When V > V_c+ (7.2 V), the off current turns on abruptly implying the creation of a persistent domain wall via local domain 180^o switching in formation of antiparallel polarization within the cell previously poled at -12 V. After the formation of antiparallel domain patterns after poling at +12 V, the off current turns on again at voltages above an onset voltage of 1.8 V (V_on < V_c+) due to the volatile domain switching within the thin interfacial layers. Reprinted with permission^[47]. Copyright 2020, Springer Nature. (E) The working principle of the mesa-structured memory cell with two side electrodes fabricated on the surface of an X/Y-cut LN single-crystal film bonded to a silicon substrate. Nonvolatile bulk domain walls (b-DW) can encode the data in contrast to the volatile domain walls (i-DW) within the interfacial layers that work as an embedded selector.